Power Performance Architect, Senior Staff - Accelerator Design

📋 Description

• • As a Power Performance Architect, Senior Staff in Accelerator Design at d-Matrix Corporation, you will play a critical role in advancing the company’s mission to unleash the potential of generative AI through cutting-edge hardware and software innovation. Your work will directly impact the power efficiency and performance of AI accelerators, enabling scalable and sustainable AI technologies.
• • Day to day, you will conduct pre-silicon power estimation for design blocks using both RTL and physical design methodologies, collaborate with front-end and DV engineers to identify power activity windows, and ensure feedback from power analysis is implemented to optimize design. You will build architectural power estimation tools for AI workloads, integrating system configuration, die-level metrics, memory bandwidth, and gate counts to model power consumption accurately.
• • You will work closely with frontend architects and backend design teams to compile performance monitor data, system requirements, and usage patterns, using your analysis to enhance hardware capabilities and guide die modifications for performance monitoring and boosting features. Additionally, you will design micro-architecture and RTL, perform synthesis, logic, and physical power performance verification using leading-edge CAD tools and semiconductor process technologies, and implement power-saving and monitoring functions to support efficient design, test, debug, and silicon bring-up.
• • d-Matrix fosters a culture of respect, collaboration, humility, and direct communication, valuing diverse perspectives to drive better solutions. The company is at the forefront of AI hardware innovation, offering a hybrid work model requiring 3–5 days onsite at its Santa Clara headquarters. You will join a mission-driven team passionate about solving complex challenges and shaping the future of AI through technical excellence and execution.
• • In this role, you will deepen your expertise in low-power ASIC design, architectural power modeling, and performance optimization for AI accelerators. You will gain hands-on experience with industry-leading EDA tools, contribute to silicon bring-up and validation, and influence the design of next-generation AI hardware. This position offers the opportunity to grow as a technical leader in a high-impact, fast-paced environment where your work directly enables breakthroughs in AI infrastructure.