Physical Design Engineer

📋 Description

• • Intel Corporation is seeking a highly skilled and motivated Physical Design Engineer to join our dynamic team in New Delhi, India, with the flexibility of remote work. This pivotal role is central to the creation of cutting-edge custom IP and System-on-Chip (SoC) designs, transforming Register Transfer Level (RTL) code into a manufacturing-ready design database (GDSII).
• • As a Physical Design Engineer, you will be instrumental in executing all phases of the physical design flow. This encompasses critical stages such as logic synthesis, where your expertise will ensure the efficient translation of logical designs into physical layouts. You will meticulously manage place and route operations, strategically positioning and connecting components to optimize performance and minimize area. Clock tree synthesis (CTS) will be a key responsibility, ensuring precise and reliable clock distribution across the entire chip, which is paramount for timing accuracy and signal integrity.
• • Your role will extend to floor planning, where you will define the overall layout and arrangement of functional blocks, power domains, and I/O interfaces. Static Timing Analysis (STA) will be a continuous activity, where you will rigorously analyze and optimize timing paths to meet stringent performance targets. This includes managing setup and hold time violations, ensuring the design operates reliably at the target frequency.
• • You will also be responsible for the design and implementation of robust power and clock distribution networks, ensuring stable and efficient power delivery throughout the chip. Reliability analysis will be a core component, focusing on mitigating potential failure mechanisms and ensuring long-term operational integrity. Furthermore, you will conduct comprehensive power and noise analysis to identify and resolve issues that could impact performance and stability, such as voltage drop (IR drop) and ground bounce.
• • A significant part of your contribution will involve verification and signoff activities. This includes performing formal equivalence verification to confirm that the synthesized netlist accurately matches the RTL design. You will conduct extensive STA to achieve timing closure, ensuring all timing constraints are met. Reliability verification will be performed to guarantee the design's robustness under various operating conditions. Static and dynamic power integrity analysis will be crucial for ensuring consistent power delivery and minimizing power-related issues.
• • Layout verification, including Electrical Rule Checking (ERC) and Design Rule Checking (DRC), will be performed to ensure the physical layout adheres to manufacturing constraints and electrical specifications. Structural design checking will also be a part of your responsibilities, ensuring the integrity and correctness of the design's structure.
• • You will be expected to analyze the results of these verification steps, identify violations, and propose effective solutions to fix them. This requires a deep understanding of both the design's architecture and the physical implementation process. Your recommendations will directly influence current and future product architectures, contributing to Intel's technological advancements.
• • Expertise in various aspects of structural and physical design is essential. This includes a strong understanding of physical clock design techniques, advanced timing closure methodologies, coverage analysis, and managing multiple power domains. Proficiency in placing, routing, synthesis, and Design for Test (DFT) using industry-standard Electronic Design Automation (EDA) tools is a must.
• • A key objective of this role is to optimize the design to enhance critical product-level parameters such as power consumption, operating frequency, and silicon area (PPA). You will continuously seek opportunities to improve these metrics, directly impacting the performance and cost-effectiveness of Intel's products.
• • Beyond execution, you will actively participate in the development and enhancement of physical design methodologies and the automation of design flows. This involves contributing to best practices, exploring new tools and techniques, and scripting to improve efficiency and reduce turnaround time.
• • This role offers a unique opportunity to work on state-of-the-art semiconductor designs, contributing to Intel's leadership in the technology industry. You will collaborate with cross-functional teams, including RTL designers, verification engineers, and layout engineers, to achieve project goals.
• • The ideal candidate will possess a strong analytical mindset, excellent problem-solving skills, and a passion for semiconductor design. You should be adept at working independently and as part of a team, with strong communication skills to effectively convey technical information.
• • This position is classified as Regular, with Shift 1 (India) working hours. The primary location is New Delhi, India, with the option for remote work, offering flexibility and work-life balance.