Senior Runtime Software Engineer

📋 Description

• • d-Matrix Corporation is at the vanguard of generative AI, dedicated to unlocking its transformative potential across the technology landscape. We are a dynamic company pushing the boundaries of both software and hardware innovation, driven by a culture of profound respect, open collaboration, and a commitment to direct communication. Our team thrives on inclusivity, recognizing that diverse perspectives are the bedrock of superior solutions. We are actively seeking individuals who are not only passionate about confronting complex challenges but are also deeply motivated by execution and tangible results. If you are ready to discover your professional playground and contribute to shaping the boundless possibilities of AI, we invite you to join us.
• • As a Senior Runtime Software Engineer in our Sydney, Australia office, you will play a pivotal role in architecting, developing, and validating the core runtime software and firmware for d-Matrix's groundbreaking AI inference processor. This innovative silicon is engineered to dramatically accelerate Natural Language Processing (NLP), vision, and recommendation workloads within data center environments. The processor's unique architecture features an in-memory compute subsystem, adeptly handling both fixed-point and floating-point data types, and supporting both dense and sparse matrix processing modes. Our foundational work includes the successful development of a CMOS test chip and validation of the architecture using real-world inference workloads compiled from PyTorch, demonstrating the viability and power of our approach.
• • Your primary responsibility will be the holistic management of the runtime performance of our silicon product. This entails the architectural design, meticulous documentation, and robust development of the runtime firmware that will execute across the chip's multiple on-chip multi-core CPU subsystems. This critical firmware will govern all facets of the AI subsystems, meticulously designed to achieve maximum hardware utilization. Key performance indicators for your success will include achieving high overall AI hardware utilization, effectively minimizing communication bottlenecks between components, and optimizing the efficient use of on-chip memory resources.
• • A significant part of your role will involve software bring-up on FPGA platforms, which will host emulated images of the embedded CPU subsystems. You will leverage JTAG-connected IDEs for debugging, ensuring the stability and functionality of the software. Furthermore, you will be instrumental in developing a firmware solution that can be rigorously developed and tested independently, even before the AI subsystem hardware becomes fully available, enabling parallel development streams and accelerating our time-to-market.
• • You will be entrusted with determining delivery schedules for your software components and ensuring strict adherence to d-Matrix's coding standards and development methodologies. A crucial aspect of this role is close collaboration with our hardware teams. You will interpret intricate hardware specifications, provide insightful feedback for design improvements aimed at enhancing utilization, throughput, and power efficiency, and work hand-in-hand to bridge the gap between hardware capabilities and software potential.
• • Collaboration extends across our global software teams, including colleagues in Australia and the US, as well as with the software quality and test teams located in the US and India. You will also engage with the hardware verification team to provide support for SoC-level design verification (DV) simulations and emulation efforts, ensuring a cohesive and thoroughly validated product.
• • Your development and debugging activities will take place on FPGA-based systems that incorporate the CPU subsystems, as well as on SystemC models that simulate the AI subsystems and the overall System-on-Chip (SoC). You will also be involved in porting the developed software to advanced emulation systems, such as Veloce or Palladium, which host the final Register Transfer Level (RTL) design, providing a high-fidelity environment for final validation.
• • A key phase of your work will be the direct involvement in bringing up the software on the actual AI subsystem hardware and rigorously validating both silicon and software performance against defined benchmarks and targets. This hands-on validation is crucial for confirming the successful implementation of our architectural vision and the achievement of desired performance metrics.
• • This role offers a unique opportunity to be at the forefront of AI hardware-software co-design, influencing the development of next-generation AI inference technology. You will contribute to a product that has the potential to redefine the performance and efficiency of AI computations in critical data center applications.