SDK Hardware Simulator Engineer

📋 Description

• • Architect, design, and deliver high-fidelity C++17/20 and Python-based hardware simulators that mirror every nuance of Innatera’s neuromorphic processors, CPUs, memory subsystems, DMA engines, and peripheral blocks—enabling software teams to develop, profile, and optimize applications months before first silicon is taped out.
• • Translate dense RTL specifications, micro-architectural documents, and power/performance spreadsheets into modular, test-driven software models that compile and run on Linux, macOS, and Windows, exposing clean APIs for internal SDK libraries and external customer tools.
• • Build and extend a scalable simulation framework that supports cycle-accurate, approximate-timed, and fast-functional modes, letting firmware engineers validate boot flows, driver teams stress-test DMA pipelines, and ML researchers benchmark spiking-neural-network workloads at 1000× real-time speed.
• • Own the continuous integration and regression suite for the simulator: craft unit tests with GoogleTest, integration tests with pytest, and nightly performance benchmarks that gate every pull request, ensuring that each code change preserves bit-exact behavior and meets latency/throughput budgets.
• • Partner daily with digital-design, verification, firmware, and SDK teams in agile sprints; review waveforms, annotate micro-ops, and iterate on register-level accuracy so that pre-silicon software behaves identically to post-silicon hardware—eliminating costly respins and accelerating customer time-to-market.
• • Deliver polished, well-documented SDK packages (CMake-based build system, pip wheels, Docker images) that allow application developers to swap between virtual and physical hardware with a single compile-time flag, dramatically shortening the feedback loop for edge-AI product teams worldwide.
• • Profile and optimize the simulator’s runtime performance using SIMD intrinsics, multi-threading, and lock-free queues, targeting 5× speed-ups per release while keeping memory footprint under 512 MB for a 1-million-neuron network—critical for CI pipelines running on cloud instances.
• • Contribute to Innatera’s open-source simulation extensions, write technical blogs, and present at conferences to evangelize neuromorphic computing, positioning the company as the de-facto standard for ultra-low-power edge AI.
• • Champion a culture of code quality: enforce clang-tidy rules, conduct rigorous peer reviews, mentor junior engineers, and maintain a living architecture document that evolves alongside the chip roadmap.
• • Influence product strategy by feeding simulation-derived power, latency, and accuracy metrics into hardware–software co-design reviews, ensuring that every architectural decision maximizes real-world application performance and energy efficiency.