
Job Overview
Location
Santa Clara
Job Type
Full-time
Category
Backend Engineer
Date Posted
March 28, 2026
Full Job Description
đź“‹ Description
- • As a Senior Emulation Engineer (L3) at d-Matrix Corporation, you will play a critical role in enabling the development and validation of next-generation AI accelerators by building and maintaining high-fidelity emulation environments that bridge hardware design and software verification, directly contributing to the company’s mission of unlocking generative AI’s potential through innovative silicon.
- • You will design, implement, and maintain advanced emulation flows using industry-standard platforms such as Palladium/Protium, ZeBu/HAPS, or Veloce, leveraging Speedbridge, UVM testbenches, and DPI-based C/C++ transactors to enable seamless co-emulation and hardware-software integration for complex SoC validation.
- • Your day-to-day responsibilities will include bringing up SoC designs on emulation/prototyping platforms, with a focus on high-speed I/O interfaces like PCIe and DDR, ensuring timing closure, signal integrity, and functional correctness across multiple abstraction layers.
- • You will collaborate closely with Design Verification, Silicon Validation, and Software teams to debug system-level issues, validate firmware and OS bring-up sequences, and enable early software development on pre-silicon emulation environments.
- • You will develop and maintain automation scripts in Python and Perl to streamline emulation setup, regression execution, waveform analysis, and result reporting, improving team efficiency and reducing turnaround time for validation cycles.
- • You will contribute to the continuous improvement of emulation methodology by identifying bottlenecks, proposing enhancements to testbench architecture, and sharing best practices across teams to elevate the overall verification productivity and quality.
- • You will work within a culture of humility, direct communication, and inclusive collaboration at d-Matrix, where diverse perspectives are valued and innovation is driven by execution-focused problem-solving in a hybrid work environment (3 days onsite in Santa Clara).
- • In this role, you will deepen your expertise in complex SoC emulation, gain exposure to cutting-edge AI hardware architectures, and become a trusted technical leader in pre-silicon validation — positioning yourself at the forefront of AI infrastructure innovation.
🎯 Requirements
- • BSEE with 5+ years of industry experience, or MSEE in Electrical Engineering with 3+ years of hands-on experience working with emulation or prototyping platforms such as Palladium/Protium, ZeBu/HAPS, or Veloce.
- • Proven experience with HSIO (PCIe, DDR) bring-up and firmware/OS bring-up on emulation or prototyping environments, including SCE-MI or co-emulation flows.
- • Strong understanding of SystemVerilog, UVM, C/C++, and waveform debugging in emulation/verification environments, with proficiency in writing automation scripts using Python and Perl.
🏖️ Benefits
- • Opportunity to work on cutting-edge AI hardware technology at the forefront of generative AI innovation, directly impacting the performance and scalability of next-generation AI accelerators.
- • Hybrid work model with 3 days per week onsite at d-Matrix’s Santa Clara headquarters, balancing collaboration with flexibility.
- • Inclusive, respect-driven culture that values humility, direct communication, and diverse perspectives, fostering an environment where technical excellence and personal growth thrive together.
- • }
Skills & Technologies
About d-Matrix Corporation
d-Matrix designs silicon for high-efficiency AI inference at scale. Its Corsair compute platform combines in-memory computing with a digital approach to slash latency and energy use in transformer and generative workloads. Targeting hyperscale data centers and edge deployments, the company offers hardware and software stacks that integrate into existing AI pipelines. Founded in 2019 and headquartered in Santa Clara, California, d-Matrix serves cloud and enterprise customers seeking cost-effective alternatives to GPUs for large language model serving.
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