Analog Design Engieer (L4/L5)

d-Matrix Corporation

Job Overview

Location

Santa Clara

Job Type

Full-time

Full Job Description

📋 Description

• As an Analog Design Engineer (L4/L5) at d-Matrix Corporation, you will play a critical role in advancing the company’s mission to unlock the potential of generative AI through cutting-edge hardware innovation, specifically by designing analog-mixed signal integrated circuits that power AI inference accelerators and high-speed die-to-die interfaces, directly enabling scalable, low-power computing for next-generation AI workloads.
• You will independently lead the design, simulation, verification, and optimization of complex analog and mixed-signal blocks — including phase interpolators, clocking circuits, PLLs, and high-speed I/O — using industry-standard Cadence and Synopsys tools, ensuring robust performance across process-voltage-temperature (PVT) corners and six-sigma Monte Carlo yield targets, while collaborating closely with layout and backend teams to achieve silicon success.
• You will be part of a collaborative, inclusive, and execution-driven team at d-Matrix’s Santa Clara headquarters, where humility, direct communication, and diverse perspectives are valued as catalysts for solving some of the most challenging problems in AI hardware, and where your contributions will directly impact the bring-up, characterization, and production readiness of silicon for real-world AI inference applications.
• In this role, you will deepen your expertise in deep sub-micron analog design (4nm and below), gain hands-on experience with full-chip AI accelerator architectures, and develop leadership skills in cross-functional technical collaboration — positioning you at the forefront of the AI hardware revolution while building a legacy of innovation in in-memory compute and high-speed interconnect technologies.
• What You Will Do:
• Design analog-mixed signal integrated circuits using Cadence and Synopsys tools for AI inference accelerators, focusing on in-memory compute engines and high-speed die-to-die interfaces.
• Perform schematic capture, SPICE simulations, Monte Carlo analysis, and system-level performance modeling to validate circuit behavior under PVT variations.
• Develop and maintain test benches for functional verification and characterization, ensuring design robustness and yield optimization.
• Guide layout engineers in deep sub-micron layout practices (4nm and below), providing feedback on parasitic extraction, matching, and symmetry to achieve power, speed, and area targets.
• Conduct independent minor layout tweaks when necessary to resolve DRC/LVS issues or improve performance without compromising design intent.
• Collaborate with backend engineers on design/layout integration, providing accurate circuit models for post-layout verification and sign-off.
• Participate in evaluation board design for silicon bring-up, including bench debug, characterization, and test feature development.
• Build and maintain automation scripts for silicon bring-up, test sequencing, and feature validation to accelerate bring-up cycles.
• About the Team or Company:
• d-Matrix is a mission-driven company at the forefront of AI hardware innovation, dedicated to transforming generative AI through software-hardware co-design, with a culture rooted in respect, collaboration, humility, and direct communication.
• The engineering team values diverse perspectives and inclusive teamwork, believing that the best solutions emerge from humble expertise, kindness, dedication, and a shared willingness to tackle hard problems together.
• What the Person Can Learn or Achieve in This Role:
• Master advanced analog design techniques in cutting-edge process nodes (4nm and below), including high-speed signaling, PLL/DLL design, and noise-sensitive mixed-signal circuits for AI accelerators.
• Gain end-to-end ownership of silicon lifecycle contributions — from concept and simulation to layout guidance, bring-up, characterization, and production readiness — while contributing to patents, publications, and industry-standard contributions in AI hardware.

🎯 Requirements

• BS/MS/PhD in Electrical Engineering with 14+ years (BS), 12+ years (MS), or 10+ years (PhD) of professional experience in high-speed circuit design blocks such as phase interpolators, clocking, and PLLs.
• Proficiency in Cadence and Synopsys analog design tools, including schematic capture, SPICE simulation, Monte Carlo analysis, and back-annotated simulations with extraction.
• Hands-on experience with circuit layout, extraction, and guiding layout engineers in deep sub-micron (4nm and below) process nodes to achieve low power, high performance, and six-sigma yield.
• Experience with channel modeling using MATLAB or equivalent tools for high-speed serial link design.
• Strong interpersonal, teamwork, and communication skills, with proven ability to collaborate effectively across cross-functional and cross-site teams.
• Demonstrated analytical and problem-solving abilities, with capacity to multi-task in a fast-paced, execution-oriented environment.

🏖️ Benefits

• Hybrid work model requiring 3–5 days per week onsite at d-Matrix’s Santa Clara headquarters, balancing collaboration with flexibility.
• Opportunity to work on pioneering AI hardware technology — in-memory compute and die-to-die interfaces — that directly enables the scalability and efficiency of generative AI systems.
• Inclusive, respect-driven culture that values humility, direct communication, and diverse perspectives as core to innovation and team success.
• Clear path for technical leadership and impact, with ownership over critical silicon blocks from design through bring-up and characterization.
• Exposure to cutting-edge process nodes (4nm and below) and industry-standard EDA tools, accelerating expertise in advanced analog/mixed-signal design for AI accelerators.
• Commitment to equal opportunity employment and affirmative action, ensuring a fair, welcoming, and empowering environment for all employees regardless of background.

Skills & Technologies

Hybrid

Degree Required

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d-Matrix Corporation

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About d-Matrix Corporation

d-Matrix designs silicon for high-efficiency AI inference at scale. Its Corsair compute platform combines in-memory computing with a digital approach to slash latency and energy use in transformer and generative workloads. Targeting hyperscale data centers and edge deployments, the company offers hardware and software stacks that integrate into existing AI pipelines. Founded in 2019 and headquartered in Santa Clara, California, d-Matrix serves cloud and enterprise customers seeking cost-effective alternatives to GPUs for large language model serving.

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