FPGA Design Engineer, Senior Staff

📋 Description

• • d-Matrix Corporation is at the vanguard of generative AI, driving technological transformation through groundbreaking software and hardware innovation. We are seeking a highly skilled and motivated Senior Staff FPGA Design Engineer to join our dynamic team in Santa Clara, CA. This hybrid role offers the opportunity to work onsite at our headquarters three days a week, fostering a collaborative environment where respect, humility, and direct communication are paramount. Our inclusive culture thrives on diverse perspectives, enabling us to tackle complex challenges and develop superior solutions. If you are passionate about pushing the boundaries of what's possible in AI and are driven by execution, this is your playground to shape the future.
• • As a Senior Staff FPGA Design Engineer, you will play a pivotal role in designing and verifying cutting-edge FPGA-based solutions specifically tailored for d-Matrix's advanced AI inference accelerator management systems. Your responsibilities will span the entire design lifecycle, from initial specification to final implementation and verification. You will be instrumental in defining the microarchitecture of our FPGA designs, working closely with cross-functional teams and stakeholders to ensure absolute alignment with ambitious project requirements and strategic objectives.
• • A key aspect of this role involves developing a resilient dual-boot architecture, crucial for enabling robust multi-core and multi-chiplet booting processes. This will require a deep understanding of system-level design and fault tolerance. Furthermore, you will be responsible for designing and implementing critical hardware and software modules that manage platform power, monitor system health, and acquire essential telemetry data. This includes developing sophisticated interfaces to the host server's Baseboard Management Controller (BMC) via SMBus, leveraging industry-standard management protocols such as MCTP, PLDM, and SPDM to ensure seamless communication and control.
• • Your expertise will also extend to integrating RISC-V CPU cores and their associated firmware directly into our FPGA designs, a critical step in building intelligent and adaptable accelerator management systems. You will also develop an eFuse controller within the FPGA, essential for configuration and security. A significant focus will be placed on designing and integrating a secure boot solution within the FPGA, adhering strictly to NIST standards. This secure boot mechanism is vital for enabling the secure initialization and operation of d-Matrix's accelerator chiplets, safeguarding our intellectual property and ensuring system integrity.
• • Collaboration is at the heart of our success. You will work hand-in-hand with diverse teams, including hardware engineers, software developers, and system architects, to guarantee seamless hardware-software integration. Your contributions will be crucial during the hardware bring-up phase and in troubleshooting complex issues that may arise. To enhance efficiency and accelerate development cycles, you will also be tasked with authoring Python scripts to automate hardware testing and streamline various development workflows. This role demands a proactive approach, a keen eye for detail, and a passion for solving intricate engineering problems in a fast-paced, innovative environment.