Hardware Tools Engineer

📋 Description

• • OpenAI is at the forefront of developing advanced AI systems, and our Hardware organization plays a pivotal role in this mission by creating specialized silicon and system-level solutions tailored for the unique demands of cutting-edge AI workloads. We are not just building the next generation of AI-native silicon; we are also deeply involved in co-designing hardware in close collaboration with our software and research partners, ensuring tight integration with AI models. Beyond delivering production-grade silicon for OpenAI’s massive supercomputing infrastructure, our team is also responsible for innovating and developing custom design tools and methodologies. These tools are crucial for accelerating the pace of innovation and enabling the creation of hardware that is specifically optimized for AI applications.
• • As a Hardware Tools Engineer, you will be instrumental in developing and continuously evolving the critical tooling ecosystem that our hardware engineers depend on daily. This encompasses a broad spectrum of essential tools, including hardware compilers, sophisticated IR (Intermediate Representation) transformations, simulation environments, debugging utilities, and robust automation infrastructure. Your work will bridge the disciplines of software engineering, compiler theory, and practical hardware design workflows, directly influencing the speed and effectiveness with which we design and iterate on next-generation AI systems.
• • You will engage in close collaboration with a diverse group of stakeholders, including architects, RTL (Register-Transfer Level) designers, and verification engineers. Your primary objective will be to translate real-world engineering challenges and friction points into durable, scalable, and efficient tooling solutions. This collaborative approach ensures that the tools we build are not only technically sound but also directly address the practical needs of our engineering teams.
• • Key responsibilities in this role include:
• • Building and enhancing the software tooling that empowers hardware teams to operate with greater speed and efficiency. This includes developing and refining tools for compilation, IR transformations, RTL generation, simulation, debugging, and automation.
• • Extending and integrating advanced hardware compiler stacks. This involves working with frontends, IR passes, lowering stages, scheduling algorithms, and code generation to Verilog/SystemVerilog, and seamlessly connecting these components to real-world design workflows.
• • Significantly improving the developer experience and overall reliability of our toolchains. This means focusing on aspects like reproducible builds, delivering clearer and more informative error messages, reducing iteration loops for faster feedback, and establishing dependable CI (Continuous Integration) and regression infrastructure.
• • Working hand-in-hand with designers and verification engineers to identify and address their most pressing pain points by developing robust and enduring tool solutions.
• • Being prepared to dive deep into RTL code when necessary. This includes the ability to read and reason about Verilog/SystemVerilog to effectively debug issues, validate the output of our tools, and enhance the debuggability of the hardware designs themselves.
• • Demonstrating a willingness to explore the entire technology stack when required. This may involve delving into gate-level views, understanding synthesis results, and examining implementation artifacts to gain a comprehensive perspective.
• • Contributing to the optimization of PPA (Power, Performance, Area) loops by developing sophisticated analysis tools and automation for managing tradeoffs in area, timing, and power consumption. This also involves improving tooling that directly influences these critical PPA outcomes.
• • You will likely thrive in this role if you possess:
• • A proven track record of building and maintaining software, demonstrated through personal projects, internships, research, open-source contributions, or equivalent practical experience.
• • Strong foundational knowledge in Computer Science, including data structures, algorithms, debugging techniques, and software design principles.
• • Proficiency in at least one of the following programming languages: Rust, C++, or Python, coupled with a strong willingness to learn and become proficient in the others.
• • A solid understanding of digital design concepts and the ability to read and interpret RTL code written in Verilog/SystemVerilog or similar hardware description languages.
• • Familiarity with compiler concepts or IR-based design methodologies, including representations, passes, transformations, and lowering techniques, gained through academic coursework or practical projects.
• • Comfort with operating in ambiguous environments and a capacity for iterating quickly based on feedback from the users of your tools.
• • Additional skills that would be considered a strong asset include:
• • Exposure to various compiler and hardware toolchains such as XLS/DSLX, LLVM, Chisel/FIRRTL, CIRCT/MLIR, or other novel hardware description languages (e.g., HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope).
• • Hands-on experience with Verilog tooling ecosystems like Yosys/RTLIL, Verilator, Slang, or experience in developing tooling that integrates with these systems.
• • Proven experience with build and test infrastructure, including tools like Bazel, various CI systems, fuzzing techniques, and performance testing methodologies.
• • Prior work experience related to synthesis, place and route, static timing analysis, or other PPA-focused workflows.